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???????????UG?????????DFT?????????????????????????????
????????????????????Top-Down Flow????DFT????????DFT???????ddc????????????????????
?????DC???
dc_shell
???????2read_design
?
source 2read_design
???????
set hdlin_enable_rtldrc_info true; # ??RTL????# ???????set test_simulation_library "./tmax/rams.v"# ??????ORCA??read_ddc mapped/ORCA.ddc# ???????ORCAcurrent_design ORCA# ????link
????????3create_test_protocol
?
source 3create_test_protocol
???????
# ??????????# read_ddc mapped/ORCA.ddc# ???????ORCAcurrent_design ORCA# ???????set test_simulation_library "../ref/tmax/libs.v"# ??????remove_test_protocol# ????set test_default_delay 0set test_default_bidir_delay 0set test_default_strobe 40# ??????set_dft_signal -view existing_dft -type ScanClock -timing { 45 55 } -port { pclk sdr_clk sys_clk }set_dft_signal -view existing_dft -port prst_n -type Reset -active_state 0set_dft_signal -view existing_dft -port scan_en -type ScanEnable -active_state 1# ??????set_dft_signal -view existing_dft -type Constant -active_state 1 -port test_modeset_dft_signalset_dft_signal -view existing_dft -type Constant -active_state 0 -port conf_ena# ?????????read_test_protocol -section test_setup ./scripts/test_setup.spf -verbosewrite_test_protocol -output output.spf
?????????????spf????????????????pre-DFT??????????D1???????D3???????D1??????Mux???????????????????????????????internal pin???constant??????????????ATE???????????
D3??????????????????active?????????pin data?clock off???????????????????pindata??????????????????
??internal pin???constant?????????????????????????????????????????
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